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5.3 CC121 Memory Map
5.3.2 COM9026 ARCNET Interface
The COM9026 Local Area Network Controller (LANC) has been implemented to provide the
ARCNET network interface. The chip contains an internal microsequencer which performs all
of the control operations necessary to carry out the ARCNET protocol. The COM9026 contains
a 'write interrupt mask' register, a 'read status' register, and a 'write command'
register. The MPU controls the COM9026 via software, by accessing the various registers.
These actions are described in the data sheet. The next figure shows the registers of the
protocol controller.
Figure 5-1 COM9026 Registers
- RI
- Receive Inhibit - This bit, if set high, indicates that a packet has been deposited
into the RAM buffer page nn as specified by the last ENABLE RECEIVE TO PAGE nn command.
The setting of this bit can cause an interrupt if the corresponding mask bit in the
interrupt mask register and the interrupt enable bit in the board control register have
been properly setup.
No messages will be received until an ENABLE RECEIVE TO PAGE nn command is issued. After
any message is received, the receiver is automatically inhibited by setting this bit to a
logic one.
- ETS2
- Extended Time Out Status 2 - This bit reflects the current logic value of the ETS2
input pin, as determined by JB1.
- ETS1
- Extended Time Out Status 1 - This bit reflects the current logic value of the ETS2
input pin, as determined by JB1.
- POR
- Power On Reset - This bit, if set high, indicates that the COM9026 has been reset. The
setting of this bit will cause an interrupt, if the enable interrupt bit of the board
control register has been set. This bit is cleared by writing the CLEAR FLAGS command to
the command register.
- TEST
- Test - This bit is intended for test and diagnostic purposes. It will be a logic zero
under any normal operating conditions.
- RECON
- Reconfiguration - This bit, if set high, indicates that the reconfiguration timer has
timed out because the RX input was idle for 78.2 µs (typ). The setting of this bit can
cause an interrupt if the corresponding mask bit in the interrupt mask register and the
interrupt enable bit in the board control register have been properly setup.
The bit is reset low during a CLEAR FLAGS command.
- TMA
- Transmit Message Acknowledge - This bit, if set high, indicates that the packet
transmitted as a result of an ENABLE TRANSMIT FROM PAGE nn command has been positively
acknowledged. This bit should only be considered valid after the TA bit is set. Broadcast
messages are never acknowledged.
- TA
- Transmit Available - This bit, if set high, indicates that the transmitter is available
for transmitting. This bit is set at the conclusion of an ENABLE TRANSMIT FROM PAGE nn
command or upon execution of a DISABLE TRANSMITTER command. The setting of this bit can
cause an interrupt if the corresponding mask bit in the interrupt mask register and the
interrupt enable bit in the board control register have been properly setup.
The valid command bytes that can be written to the command register are showed in the
next table.
