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5.4 Local Memory Map

5.4.3 Mailbox

The first four memory locations of the shared SRAM are assigned to a mailbox. The mailbox locations 0 and 1 have interrupt capabilities and the mailbox locations 2 and 3 have reset capabilities. When a VMEbus master accesses the interrupt mailbox for write, a level 1 interrupt is generated to the local processor. The local processor uses an autovector to acknowledge this interrupt. When a VMEbus master accesses the reset mailbox for write, the CC175 (including the processor) will receive a hardware reset. Read accesses to the mailbox locations do not activate the reset or interrupt functions.

CC175 - Dual Channel Intelligent CAN Interface for VMEbus - 30 SEP 1996
Copyright © 1996 Compcontrol, Inc.

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