4.6 Change of State Circuit

This circuit is designed to generate an interrupt whenever the inputs of a channel do not match with an user defined pattern.

To accomplish this the following blocks are defined:

: 1. the input signals read from the debounce circuit outputs (U34, U36, U38, U40 and U43)
: 2. an 8 bit register (U33, U35, U37 and U39), which contents is defined by the user, identified as the Compare State Register
: 3. an 8 bit pattern comparator (U48, U49, U51 and U52) which detects differences between the outputs of the debouncer and the outputs of the Compare State Register
: 4. memory element (U50) to remember that a difference between the state of the input lines and the pattern of the Compare State Register has existed.
: 5. a sample pulse generator (U50 and U58)
: 6. a register to hold the state of the inputs when the difference was detected, identified as the Change State Register (U41, U42, U44 and U46)

Figure 4-2 Change of State Circuit

To detect a change in the input lines the pattern comparator must compare the "Real Time" input lines with a copy of the old state of the input lines. Thus a copy should be made of the present state of the input lines, by reading the Current State Register, and this data should be written into the Compare State Register.

Writing to this Compare State Register resets the memory element to a "no-interrupt" status. The output of the comparator should now be inactive (no differences). The output of the comparator will go active (a difference) as soon as one or more of the inputs change their level. The memory element is set to the "interrupt" status and asserts the interrupt request line to the BIM. Also the sample pulse generator is triggered and a sample of the outputs of the debouncer is stored in the Change State Register. Data read from this Change State Register will now reflect the state of the input lines when the change was detected.

CC92 - Isolated Digital Input Board - 3 OCT 1996

[Next] [Previous] [Up] [Top] [Contents] [Back]