3.2 Memory Map Layout

The following table shows the registers with their respective offsets to the module's base address.

Register Offsets
Offset	Contents
01	Read/Write Output Register Channel 0
03	Read/Write Output Register Channel 1
05	Read/Write Output Register Channel 2
07	Read/Write Output Register Channel 3

An output is activated when the corresponding bit in the output register is set (1). An output is de-activated when the corresponding bit in the output register is reset (0). The state of 8 outputs are defined by a single 8 bit write operation to the proper channel. The state of a single output can be changed with a bit_set or bit_clear operation on the proper output bit. The following table shows the Output Register bit assignment for the four channels.

Output Register Assignments
Channel	Bit	Output
0	0 .. 7	0 .. 7
1	0 .. 7	8 .. 15
2	0 .. 7	16 .. 23
3	0 .. 7	24 .. 31

CC94 - Isolated Output Board - 30 SEP 1996

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