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5.2.1 Channel Registers

5.2.1.7 IRQ Mask Register

Figure 5-7 IRQ Mask Register

MDI

When this bit is set, a difference between the DI bit and the CDI bit will cause an interrupt request to the Bus Interrupter Module (BIM).
When MDI=0, a change of state of the channel's DI bit will not generate an interrupt to the BIM.

MIND

When this bit is set, a difference between the IND bit and the CIND bit will cause an interrupt request to the Bus Interrupter Module (BIM).
When MIND=0, a change of state of the channel's IND bit will not generate an interrupt to the BIM.

After a SYSRESET these bits are cleared.

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