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[Previous] [Up] [Top] [Contents] [Back]5.2 Device Group Registers
A channel consists of a set of registers described in the following paragraphs. The address of the registers can be calculated by adding the 'group offset' and the 'channel offset' to the board base address.
| $00 | MSW Counter |
| $02 | LSW Counter |
| $05 | Enable Index Register |
| $07 | Index Status Register |
| $09 | Direct Input Register |
| $0B | Compare Status Register |
| $0D | State On IRQ Register |
| $0F | IRQ Mask Register |
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