5.2.1.3 Index Status Register

Figure 5-3 Index Status Register

INDS: When INDS=1, an index pulse has occurred. This bit is cleared after the Index Status Register has been read; it can only be set when the EIND bit in the 'Enable Index Register' is set.

CC133 - 12 Channel Incremental Encoder Interface With Isolated Inputs - 30 SEP 1996