5.2.1.2 Enable Index Register

Figure 5-2 Enable Index Register

EIND: When EIND=1, an index pulse will reset the counter.
When EIND=0, the index pulse is masked and will not reset the counter.
LVLIND: When LVLIND=0, a '1-0-1' pulse on the index input will clear the counter, if enabled using EIND.
When LVLIND=1, a '0-1-0' pulse on the index input will clear the counter, if enabled using EIND.

After a SYSRESET these bits are cleared.

Note: The state of the EIND bit does not affect the interrupt capability of the index input.

CC133 - 12 Channel Incremental Encoder Interface With Isolated Inputs - 30 SEP 1996