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[Previous] [Up] [Top] [Contents] [Back]5.11 Timer Interrupts
The CC175 provides a timer which generates an interrupt every 100 µs. The timer interrupts can be enabled/disabled by writing the TIENA bit at the timer interrupt register. Writing this bit to '0' enables the timer and interrupts will be generated every 100 µs. When this bit is set '1', the timer is disabled and no interrupts are generated. The local processor uses an autovector to acknowledge this interrupt.
Figure 5-9 Timer Interrupt Register
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