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Dtack is generated whenever the board is selected or when an interrupt acknowledge cycle is performed. The Dtack timer is started immediately when a channel register is selected (A4 is high). When the BIM is selected (A4 is low) the Dtack timer is started when the BIM asserts its DTACK output.
During an interrupt acknowledge cycle the Dtack timer is started when the BIM asserts its INTAE output. The Dtack timer is started by deasserting the CLRDT signal to the shift register U53. The clock input of this register is connected to the 16 Mc clock and will shift a '1' into the register. After four clock periods output 4D will go high and DTACK* is asserted on the bus.
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