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5.2.1 Channel Registers

5.2.1.1 Channel Counter Registers

When one byte is read, the encoder chip generates a load output latch pulse for the four bytes of the Counter register. From that time until the next system reset, the load output latch pulse will only be generated during a read operation if this same byte is read. Special care should be taken if reading individual bytes to ensure that these operations are always performed in the same order.

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